Designers of servers, switches and other networked devices face ever-increasing aggregate data rates. Today's DWDM backbonesdeliver 160 wavelengths at 10 Gbits/second each. Tomorrow, backbones will run at 40 Gbits/s per channel. Faced with that torrent of data, system designers will have to adopt two-dimensional optoelectronic interconnects instead of copper interconnects. Only optical interconnects can achieve the required aggregate data rates needed for high-speed rack-to-rack, board-to-board and optical-backplane data transmission in optical transport, core router, server and storage-area network applications.

But designing an optical module to address this need presents its own issues. In addition to conquering the system-level problems of speed and of routing multiple arrayed transmissions, the IC chip set and module designs require innovative solutions. While packaging and thermal considerations demand unique development options, in this article we will address the difficulties involved in maintaining the noise budget in the IC chip set and packaging.

To meet the pressing need for short-reach, highspeed optical interconnects, TeraConnect Inc (Nashua, N.H.) teamed with NurLogic Design Inc. (San Diego). TeraConnect's expertise stems from core technology developed at BAE Systems (formerly Sanders, a Lockheed Martin company). When the two companies were first introduced, TeraConnect was still part of Sanders-BAE. It approached a system OEM with its unique packaging and 2-D array technology as a solution for the OEM 's backplane for high-end routing systems. At the time, NurLogic was working with the same OEM on project proposals unrelated to the Sanders work. The OEM knew that NurLogic had strong expertise in mixed-signal IC development and recognized that the two companies would be a good match for this project.

Thus, TeraConnect developed the Terminator Series T-48, comprising two 48-channel, 2.5-Gbit/second per channel hybrid modules: a transmit module and a receive module. Each module incorporates a custom transmit or receive PMD IC designed by NurLogic Design. The T-48' 120-Gbit/s aggregate data rate targets high-density short-reach datacom applications. We will use these modules and the chip set as the design example for this article.

Module description The T-48 modules are optical/electrical (O/E) converters that operate at the first level (PHY layer) of the OSI model (see Fig.1). One module inputs 48 differential CML electrical signals and converts them to optical signals for transmitting; the other receives 48 optical signals and converts them to 48 differential CML outputs. Within the modules, the PMD ICs' 2-D arrays of laser diode drivers and PIN diode receivers are flip-chip-bonded to the 2-D arrays of oxide-confined, 850-nm VCSELs and PIN photodiodes, respectively (see Fig.2). Applications for the highly integrated modules are primarily in rack-to-rack, custom interconnects for routers, switching, servers and storage-area networks.

The NurLogic transmit and receive ICs are built using 0.25-micron SiGe BiCMOS technology. The receiver chip integrates 48 transimpedance amplifiers, 48 limiting postamplifiers and 48 CML drivers, along with bias and test circuitry. The transmitter IC contains 48 programmable laser-diode drivers, 48 CML receivers and test circuitry.SiGe was the process of choice because it allowed NurLogic to design circuits with a high PSRR and high bandwidth at low power levels. Very high-frequency SiGe transistors can be run at low bias currents yet still achieve high bandwidth. Other materials, such as GaAs, require too much power to permit encapsulating so many channels in so small a module.

Packing 48 high-speed channels into a single module posed severe challenges in noise budgeting, layout design,process selection, power distribution and consumption, thermal management and packaging. The T-48 modules are constructed using advanced, patented packaging technology developed by Lockheed Martin and now owned by TeraConnect for commercial applications.

TeraConnect developed noise and jitter specs by starting with its customers' specifications for the BER of a 2.5-Gbit/s link. A BER of 10 12 was a common specification, but many customers asked for 10 15 or lower. The BER yielded a jitter specification of 100 ps maximum for an entire link,comprising a signal coming in through the package to the transmit IC, traveling across the fiber link and back through the receive IC, and then out through the package (see Fig.3). As NurLogic progressed in its IC designs, simulations indicated that the ICs would contribute 20 ps of jitter each, so each module package had to contribute no more than 30 ps of jitter. The package and the ICs were designed in close coordination, and the companies worked together to eliminate problems.

By design, the receive IC's footprint is identical to the transmit IC's footprint (see Fig.4). That provides the advantage of allowing one package design to suffice for both the transmit and receive modules. Further, when customers do their printed-circuit board layout, routing to the Serdes IC will be simplified.

Designing the ICs Because of the strictures imposed by optical considerations, a major design challenge was the limited area for driver and receiver channels. NurLogic performed exhaustive signal-integrity simulations to ensure that noise and jitter would meet the specification. The ICs' layouts make use of metal shielding and zone biasing to ensure that all the circuits are properly configured for local supply variations. An integrated power-distribution methodology was used to manage the power-supply distribution and resistive losses. Test circuitry was also included, to allow the silicon to be verified before assembly.

Relying on extensive experience in analog, digital and microwave design, NurLogic partitioned the ICs 'designs and established noise and jitter budgets for each partition.

Differential signaling with shielding between signal pairs to reduce RF emissions was chosen for all data paths on the ICs. Comprehensive RF simulations using Pittsburgh-based Ansoft's HFSS were performed on the connector interface and the connections to the die. The goal was to have a low return loss and to reduce the amount of jitter generated by the package's interface to the die. RF simulations on crosstalk between signal pairs were also performed to achieve the goal of reducing crosstalk below -30 dB. The ICs achieved an 11 of better than -20 dB.

Parasitic extraction was done both in-house and by OEA International (Santa Clara, Calif.)under contract. OEA 's extractions were used as a check on in-house extractions. The Diva and Assura tools from Cadence Design Systems (San Jose,Calif.) were used for in-house extractions. Armed with the extracted resistances and capacitances, Cadence's Analog Artist was used to simulate the whole IC.

TeraConnect created an interconnect model starting with the pads of the IC and progressing through the entire package, including wire bonds and vias. The model also included 8 inches of trace on an FR4 printed-circuit board to simulate the customer's connection to a Serdes IC. The idea was to include enough margin to account for the customer's interconnects, vias and discontinuities.

TeraConnect's simulation model used ADS, from Agilent Technologies (Palo Alto,Calif.), which has both frequency-domain and time-domain capability. One goal was to achieve a strong correlation between measurements in the lab and the results of simulations. The designers did several iterations of building a module and testing their models and refining them until their measurements approached predictions.

VCSELs and PIN photodiodes A VCSEL is an extremely small laser, about 3 microns long (that is, approximately 1/10,000 inch). A VCSEL consists of two mirrors that are formed parallel to the surface of the die, sandwiching an active region. The mirrors reflect the light generated in the active region. The reflections back and forth result in stimulated emission, providing emitted coherent light at a single wavelength.

VCSELs are semiconductor lasers that emit a circular, low-divergence beam perpendicular to their p-n junction. In a VCSEL, light propagates vertically rather than laterally through the structure as with edge-emitting semiconductor lasers. With the vertical orientation, the laser cavity can be grown to match the wavelength of laser light. With such a small cavity, the gain-bandwidth of the device supports only a single longitudinal mode. VCSELs are the only lasers that are arrayable in 2-D arrays using photolithographic techniques.

Because the output of semiconductor lasers varies with age and temperature, provisions had to be made for adjusting the bias and modulation currents of the lasers.

Fortunately, VCSEL technology has matured to the point where the devices have well-understood output-power and threshold-current variations over a wide operating-temperature range and over their service lifetime.

Based on those well-defined characteristics, the T-48 transmit module features built-in programmability of the VCSELs' modulation and bias currents. An on-board microcontroller in the module does the programming, requiring no control or monitoring from the system. The lasers' safety compliance meets Class 3A FDA and Class 3A IEC requirements.

A PIN photodiode is a solid-state device that converts light into electric current. Photodiodes are typically sensitive to light in the spectral range from about 200 nm (near UV) to about 1,100 nm (near IR). A photodiode's response is usually linear within a few tenths of a percent from the minimum detectable incident light power up to several milliwatts.

Response linearity improves with increasing applied reverse bias and decreasing effective load resistance. Heating a photodiode shifts its spectral-response curve (including the peak)toward longer wavelengths. Conversely, cooling shifts the response toward shorter wavelengths. Consequently, PIN photodiodes need a postamplifier to level their response over input-level and temperature variations.

The T-48 is a half-duplex, asynchronous module with an aggregate bandwidth of 120 Gbits/s and can operate over ranges of 300 meters using 50-micron core multimode fiber or 100 meters using 62.5-micron core multimode fiber. The 48 optical signals are coupled to a T-48 module via a pair of 2 x 12 MPO industry-standard connectors.A T-48 module is a 600-pin pluggable BGA. The majority of the pins are power and ground pins, to ensure the highest signal integrity.

The T-48 modules measure only 2 x 3 x 0.5 inches, fitting easily into the CompactPCI form factor using standard pc-board spacing. They require +2.5-V and +3.3-V supplies for their mixed-signal circuitry and current-mode logic. The 48 optical channels are arranged as four independent 1 x 12 arrays, allowing system designers to economize power consumption by powering up or down any rows as needed (see Fig.5).

Dissipating a nominal 6 W in the transmitter module and 8 W in the receiver module, the T-48s require no special cooling provisions (see Fig.6). They come with heat spreaders, allowing designers to custom-fit heat sinks of their choice, provided the case temperatures stay within their 0° C to 80° C operating range.